The 6821 Peripheral Interface Adaptor (PIA)

The PIA interfaces to the 6800 microprocessor with an 8-bit bidirectional data bus, three chip select lines, two register select lines, two interrupt request lines, a read/write line, an enable line and a reset line. To ensure proper operation with the 6800 rnicroprocessor, VMA should be used as an active part of the address decoding.


The complete 6821 data sheet is available as a PDF document.

                  Block Diagram of the 6821 Peripheral Interface Adaptor (PIA)


The internal registers are selected using the following table 1:

Bit 2 in each Control Register CRA-2 and CRB-2 determines selection of either a Peripheral Register or the corresponding Data Direction register, when the proper register select signals are applied to RS0 and RS1.  A '1' in bit 2 position selects the Peripheral register and a '0' in the bit 2 position selects the Data Direction register.